It is well known to use electroless plating for applying metal contacts to semiconductors. Generally, there are two problems that must be overcome, residual interfacial oxide and non-uniform plating. Various techniques have been developed in the prior art to attempt to overcome these problems.
U.S. Pat. No. 3,535,176 describes electroless plating of nickel on silicon surfaces exposed in oxide windows. Residual oxide in the window interferes with the electroless plating and/or produces high contact resistance. Residual oxide is removed prior to plating by heating the wafer to 400.degree.-600.degree. C. and evaporating or sputtering an active metal (e.g., Al or Ti) on the surface to reduce the residual oxide and act as an oxygen scavenger. The metal and scavenged oxide are etched away and the electroless nickel plating applied.
In U.S. Pat. No. 3,453,501, semiconductor contacts are provided by first vapor depositing and sintering a thin Al layer, second vapor depositing and sintering a thin Ag layer, and then applying nickel by electroless plating.
U.S. Pat. No. 3,711,325 describes preparation of semiconductor surfaces for electroless nickel plating by first activating the surfaces by immersion in aqueous HF containing 10 ppm Au.sup.+3 and then quickly transferring it to the electroless nickel plating bath. The HF solution removes any residual oxide and leaves behind sufficient Au ions to promote uniform electroless nickel deposition.
In U.S. Pat. No. 3,949,120, electrical contacts are to an N.sup.+ PP.sup.+ silicon structure formed by diffusing phosphorous and boron into opposite faces of a P-type starting wafer and then, on both sides of the wafer, (i) applying a first electroless Ni layer from an aqueous solution containing nickel chloride and sodium perphosphate, sintering the Ni layer between 300.degree.-950.degree. C. to form nickel silicide, (ii) applying a second electroless Ni layer, (iii) applying an electroless Au layer over the second Ni layer and sintering at 800.degree.-1200.degree. C. to drive Ni and Au into the semiconductor substrate, (iv) applying a third electroless Ni layer on the preceding layers, and (v) applying a second Au layer on the third Ni layer.
In U.S. Pat. No. 4,419,390, non-plateable semiconductor surfaces are rendered plateable by first immersing the semiconductor in a nucleation promoter containing Ni, Co, Fe, or Cu ions and a reducing agent capable of chemically interacting with both with the semiconductor and these metal ions in the promoter solution to the metallic state. This pre-treatment forms nucleation sites which catalyze the subsequent electroless deposition.
U.S. Pat. Nos. 3,772,078 and 3,772,056 describe enhancement of electroless plating of various non-semiconductor substrates by pre-treatment of the surfaces with metallic salts which on exposure to radiant energy or aqueous chemical reducing agents are converted to a layer of metal nuclei which is non conductive but capable of catalyzing the subsequent electroless plating reaction.
U S. Pat. Nos. 3,993,491 and 3,993,799 describe enhancement of electroless plating of various non-semiconductor dielectric substrates by coating the surface with a hydrous oxide colloid of precious metal ions or aqueous solution of stannous or copper ions, followed by contacting the surface with an aqueous reducing agent capable of reducing the valence state of the metal ions, followed by immersion in the electroless plating bath.
The foregoing U.S. patents are incorporated herein by reference. Another way to enhance electroless plating of semiconductor surfaces is to use surfaces that are microscopically rough, e.g., have large numbers of atomic lattice defects in the surface that can act as nucleation sites.
The above-mentioned prior art electroless plating techniques suffer from a number of limitations well known in the art, especially when applied to semiconductor substrates. For example, unlike many dielectric or metal surfaces, the tendency of semiconductor surfaces to react in the electroless plating bath is dependent on the semiconductor doping level. For example, a plating bath which is effective in plating a P-type surface may not be effective in plating an N-type surface and vice-versa. The higher the doping level the greater the effect. This can be overcome by using surfaces that are sufficiently rough (microscopically) so that the selective plating effect is overwhelmed by the number of nucleation sites provided by the surface structural defects.
While the selective plating effect has not been important or often not even recognized in the past because of the comparatively high level of inherent surface defects, this is no longer true. There is now an increasing desire to minimize surface defects, even those minute surface defects that can act as nucleation sites for plating. Semiconductor wafers are now being polished to degrees of smoothness and surface perfection that were unheard of a few years ago. Thus, a need continues to exist for improved methods of surface activation for electroless plating of semiconductors, especially where oppositely doped regions are present on very smooth substrates.
As used herein, the words "metal salt" or "metal salts" are intended to refer to any reducible metal or semiconductor bearing compound, including but not limited to organic or inorganic metal and/or semiconductor compounds. Non- limiting examples are metal or semiconductor halides and silanes.